The invention relates generally to the characterization of common clock timing margins. The invention relates more particularly to the characterization of common clock timing margins using jitter analysis.
Jitter is the displacement or deviation of some aspect of the pulses in a high frequency digital signal. The deviation can be in terms of amplitude, phase timing, or the width of the signal pulse. Another definition of jitter is the period frequency displacement of the signal from its ideal location. Among the causes of jitter are electromagnetic interference and crosstalk with other signals. Jitter can cause a display monitor to flicker, affect the ability of the processor in a personal computer to perform as intended, introduce clicks or other undesired effects into audio signals, and cause the loss of transmitted data between network devices. The amount of jitter that is allowable varies greatly and depends on the particular application.
Clock jitter is cycle to cycle variation in the clock period. The net effect of clock jitter is that it can reduce the total delay that signals are allowed to have for a given frequency target (i.e. jitter can reduce the clock cycle time, as illustrated in FIG. 1A-FIG. 1E). Causes of clock jitter include system noise that affects the response of clock driver circuits and system noise that affects the transmission characteristics of signals. Since this noise may affect the operation of a system, jitter must be considered in system analysis.
Electronic systems characteristically exhibit noise as a function of signal frequency at discrete and identifiable locations along a frequency spectrum. These points provide a signature of the systems sensitivity to signal stimulus at a given frequency. This signature may be used to characterize jitter introduced onto clock signals as a result of the noise that is exhibited. However, a complete characterization of the introduction of jitter onto clock signals resulting from the noise exhibitions cannot be made using such signatures. This is because the limited points of jitter introduction corresponding to the limited points of noise exhibition reflected in such signatures provide an incomplete picture of a systems sensitivity to noise. As a result, the usefulness of such signatures is limited as a jitter analysis tool.
As suggested above, introducing jitter onto a clock signal and characterizing it once introduced is one method of analyzing jitter. A prior art method of introducing jitter to a clock signal is illustrated in FIG. 1F. This figure illustrates the introduction of jitter by the removal of decoupling capacitors from the clock driver. FIG. 1F shows a clock driver chip. Each of the circles shown therein identifies a 3.3V supply pin. Intel""s(trademark) reference platforms recommend a 0.1 uF capacitor between each pin and ground. The removal of some of these capacitors will increase the output clock jitter, but not predictably. Removal of decoupling capacitors also directly impacts output edge rates. As a result, all timing must be re-tested and validated for the clock driver when decoupling is reduced.